The doi above is for this specific version of this dataset, which is currently the latest. Newer versions may be published in the future. For a link that will always point to the latest version, please use
doi: 10.4121/09195299-6318-4e2f-8542-2bd945a9688c

Singh, Abhairaj (2024): Data and code underlying the research of: Robust logic for STT based CIM. Version 1. 4TU.ResearchData. dataset. https://doi.org/10.4121/09195299-6318-4e2f-8542-2bd945a9688c.v1

Dataset

• Electrical and Electronic Engineering
• Engineering

computation in memory, logic, sense amplifier, stt-mram

CC0

RefWorks, BibTeX, Reference Manager, Endnote, DataCite, NLM, DC, CFF

by Abhairaj Singh

This work targets BNN-related applications. Given the inherent low sensing margins due to low TMR of STT devices, this work proposes an adaptive referencing mechanism to improve the sensing margin while performing logic operations in an STT-MRAM-based CIM. Reference signals are generated using multiple STT-MRAM devices and placed strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. The concept is demonstrated using an STT-MRAM model, which is calibrated using 1Mb characterized array at IMEC and is validated by deploying it in a BNN. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

• 2024-02-16 first online, published, posted

4TU.ResearchData

g-zipped shape files, pdfs, xlsx, mat

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

• https://ieeexplore.ieee.org/document/8050923
• https://ieeexplore.ieee.org/document/8241447

• MNEMOSENE (grant code 780215) EC Horizon 2020 Research and Innovation

TU Delft, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Department of Computer Engineering
IMEC