Data and code underlying the research of: SRIF-ADC for CIM accelerators
doi: 10.4121/08622fc8-fb07-4b1d-b875-c0be17962b01
CC0This targets neuromorphic and general-purpose arithmetic applications. A scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringent power and area constraints. Techniques to stabilize the node receiving analog in-
puts are implemented that allow more rows to be activated at the same time, thereby improving the scalability in terms of higher parallelism of operations. A self-timed variation-aware design approach is introduced along with design measures to drastically reduce the read disturb of memristor devices. In addition, a compact, built-in sample-and-hold circuit to replace the typically used large-sized capacitance is present along with a built-in weighting technique to alleviate the need for post-processing when combining outputs of different bit significance. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.
- 2024-02-16 first online, published, posted
- MNEMOSENE (grant code 780215) EC Horizon 2020 Research and Innovation
DATA
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14,254 bytesMD5:
48434b025699dae33b2842eb800b9ad8Y2021_TCAS1_Readme.docx -
1,369,918 bytesMD5:
a87ce6a12806ed5c2c53b63fda4ee377Y2021_TCAS1.zip - download all files (zip)
1,384,172 bytes unzipped
