Data and code underlying the research of: SRIF-ADC for CIM accelerators

doi: 10.4121/08622fc8-fb07-4b1d-b875-c0be17962b01.v1
The doi above is for this specific version of this dataset, which is currently the latest. Newer versions may be published in the future. For a link that will always point to the latest version, please use
doi: 10.4121/08622fc8-fb07-4b1d-b875-c0be17962b01
Datacite citation style:
Singh, Abhairaj (2024): Data and code underlying the research of: SRIF-ADC for CIM accelerators. Version 1. 4TU.ResearchData. dataset.
Other citation styles (APA, Harvard, MLA, Vancouver, Chicago, IEEE) available at Datacite
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This targets neuromorphic and general-purpose arithmetic applications. A scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringent power and area constraints. Techniques to stabilize the node receiving analog in-

puts are implemented that allow more rows to be activated at the same time, thereby improving the scalability in terms of higher parallelism of operations. A self-timed variation-aware design approach is introduced along with design measures to drastically reduce the read disturb of memristor devices. In addition, a compact, built-in sample-and-hold circuit to replace the typically used large-sized capacitance is present along with a built-in weighting technique to alleviate the need for post-processing when combining outputs of different bit significance. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

  • 2024-02-16 first online, published, posted
g-zipped shape files, pdfs, xlsx, mat
  • MNEMOSENE (grant code 780215) EC Horizon 2020 Research and Innovation
TU Delft, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Department of Computer Engineering


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