%% Figure 3a
Vsd: Source-drain voltage in mV
Vp: BS gate voltage in mV
dI: Lock-in current in A.

An offset from the measurement electronics of 0.06 mV should be subtracted from Vsd. Device conductance can be obtained by dividing dI by the excitation voltage dU= 1E-4 V.


%% Figure 3b
Vsd: Source-drain voltage in mV
Vtg: TG gate voltage in mV
dI: Lock-in current in A.

An offset from the measurement electronics of 0.06 mV should be subtracted from Vsd. Device conductance can be obtained by dividing dI by the excitation voltage dU= 1E-4 V.


%% Figure 3d
Vsd: Source-drain voltage in mV
Vp: P gate voltage in mV
dI: Lock-in current in A.

An offset from the measurement electronics of 0.06 mV should be subtracted from Vsd. Device conductance can be obtained by dividing dI by the excitation voltage dU= 0.2E-4 V.


%% Figure 3e
Vp: P gate voltage in mV
dI: Lock-in current in A.

Device conductance can be obtained by dividing dI by the excitation voltage dU= 0.2E-4 V.


%% Figure 3fg
B: In-plane magnetic field in T
Vp: P gate voltage in mV
dIL Lock-in current in A.

Device conductance can be obtained by dividing dI by the excitation voltage dU= 0.2E-4 V.
Delta_Vp can be obtained by subtracting the fitted mean peak position for either the split GS or the split ES line from the Vp data.


%% Figure 3h
B: In-plane magnetic field in T
dEz_GS: Ground state splitting in uV
dEz_ES: Excited state splitting in uV