PV5 ABCversatile verification and synthesis arsenal

A System for Sequential Synthesis and Verification

Application domain/field

Type of tool

Framework for synthesis and verification of boolean networks

Expected input

Binary logic circuit/network

Format:

Expected output

The output can be given in many different formats:

Internals

ABC implements several different techniques including: All of this is applied to boolean networks, i.e. directed acyclic graphs (DAGs).
Framework Model checking Synthesis

Links

Last commit date

23 January 2022

Related papers

https://doi.org/10.1007/978-3-642-14295-6_5 (CAV '10)

Related tools

SIS

ProVerB specific

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ProVerB is a part of SLEBoK. Last updated: July 2022.