| # Generated by: | Cadence Innovus 21.11-s130_1 |
| # OS: | Linux x86_64(Host ID qce-icdesign.ewi.tudelft.nl) |
| # Generated on: | Mon Jul 24 00:45:51 2023 |
| # Design: /TD> | top_chip_digital |
| # Command: | checkDesign -all -outdir ./output/top_chip_digital/init_stage/full_checkDesign/ |
| Design Name |
top_chip_digital |
| Number of cells used in the design |
100 |
| Number of Non-uniquified instances in the design |
0 |
| Cells with missing LEF |
0 |
| Cells with missing PG PIN |
0 |
| Cells with missing dimension |
0 |
| Cells dimensions not multiple integer of site |
0 |
| Block cells not covered by obstruction |
0 |
| Block cells with fixed mask has pins not colorred |
0 |
| Cells pin with missing direction |
0 |
| Cells pin with missing geometry |
0 |
| Cells PG Pins with missing geometry |
0 |
| Cells with missing Timing data |
0 |
| Annotation to Verilog Netlist |
0% |
| Annotation to Physical Netlist |
0% |
| Floating Ports |
0 |
| Ports Connect to multiple Pads |
0 |
| Ports connected to core instances |
752 |
| Output pins connected to Power Ground net |
0 |
| Instances with input pins tied together |
1 |
| TieHi/Lo term nets not connected to instance's PG terms |
0 |
| Floating Instance terminals |
0 |
| Floating IO terms |
0 |
| Tie Hi/Lo output terms floating |
0 |
| Output term shorted to Power Ground net |
0 |
| Nets with tri-state driver |
0 |
| Nets with parallel drivers |
0 |
| Nets with multiple drivers |
0 |
| Nets with no driver (No FanIn) |
0 |
| Output Floating nets (No FanOut) |
5 |
| High Fanout nets (>50) |
83 |
| Tie Hi/Lo instances connected to output |
0 |
| Verilog nets with multiple drivers |
0 |
| Dont use cells in design |
0 |
| Unplaced I/O Pins |
752 |
| Floating I/O Pins |
0 |
| I/O Pins connected to Non-IO Insts |
752 |
| Unplaced I/O Pads |
0 |
| VSS |
Unrouted |
| VDD |
Unrouted |
| Floating Power Ground terms |
0 |
| Power/Ground pins connected to non Power/Ground net |
0 |
| Power pin connected to Ground net |
0 |
| Ground pin connected to Power net |
0 |
| Off-Grid Horizontal Tracks |
0 |
| Off-Grid Vertical Tracks |
0 |
| Placement grid on Mfg. grid |
FALSE |
| User grid a multiple of Mfg. grid |
FALSE |
| User grid a multiple of Mfg. grid |
FALSE |
| Horizontal GCell Grid off Mfg. grid |
0 |
| Vertical GCell Grid off Mfg. grid |
0 |
| DIE/CORE on Grid |
FALSE |
| Core Row grid not a multiple of Mfg. grid |
0 |
| AreaIO rows not on core-grid |
0 |
| BlackBoxes Off Mfg. Grid |
0 |
| Blocks Off Mfg. Grid |
0 |
| BlackBoxes Off placement Grid |
0 |
| Blocks off placement Grid |
0 |
| Instances not snapped to row site |
0 |
| Instances not on Mfg. Grid |
0 |
| PrePlaced hard-macro pins not on routing grid |
0 |
| Class COVER cell not snapped to manufacture grid |
0 |
| Modules with off-grid Constraints |
0 |
| Groups with off-grid Constraints |
0 |
| PartitionPower Domain off Grid |
0 |
| PreRoute not on Mfg. grid |
0 |
| Off Track Pre-Routes |
0 |
| Off Grid Power/Ground Pre-routes |
0 |