cff-version: 1.2.0
abstract: "<p>This targets image classification applications. This work presents a memory-periphery co-design to perform accurate A/D conversions of analog matrix-vector-multiplication (MVM) outputs. A novel scheme is introduced where select-lines and bit-lines in the memory are virtu- ally fixed to improve conversion accuracy and aid a ring-oscillator-based A/D conversion, equipped with component sharing and inter-matching of the reference blocks. In addition, we deploy a self-timed technique to further ensure high robustness addressing global design and cycle-to-cycle variations. The concept is demonstrated using a 4Kb CIM chip prototype using resistive bitcells on TSMC 40nm CMOS technology.&nbsp;This dataset includes schematic netlist files, chip photos, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.</p>"
authors:
  - family-names: Singh
    given-names: Abhairaj
title: "Data and code underlying the research of: CCO-ADC for CIM Accelerators"
keywords:
version: 1
identifiers:
  - type: doi
    value: 10.4121/e6614bef-e325-4555-b53c-1e236b8b23cd.v1
license: CC0
date-released: 2024-02-16